The architecture for an agile world
IOb-ASRC24, 24-bit, -140dB THD+N, Multi-Channel Audio Async Sample Rate Converter
The IObundle 24-bit/-130dB THD+N Multi-Channel Audio Asynchronous Sample Rate Converter resamples the input audio digital signal, sampled at frequency Fin, and produces an output signal, sampled at frequency Fout. It uses a variable-coefficient FIR filter, a ratio estimator module to compute the conversion ratio and its inverse, a ROM&Interpolation module to compute the filter coefficients, a circular RAM block to store the input samples and an output FIFO to store the output samples. The FIR filter has order 32 for up conversions and 32/ratio for down conversions. Conversions between any two frequencies in the [8, 192] kHz range have been exhaustively tested. The design uses three clock domains. The input and output word clocks are asynchronously sampled to compute their periods and therefore the ratio and its inverse. All computation is performed in the system clock domain. The core can process tens to hundreds of Time-Division Multiplexed (TDM) audio channels, depending on the system clock frequency. The output group delay variation upon reset is less than one output sample period. The Total Harmonic Distortion plus Noise (THD+N) has an average of -140dB and is never higher than -130dB. These THD+N values are achieved after a fixed sync time of 20 ms.
IOb-UART, a RISC-V UART
The IObundle UART is a RISC-V-based Peripheral written in Verilog, which users can download for free, modify, simulate and implement in FPGA or ASIC. It is written in Verilog and includes a C software driver. The IObundle UART is a very compact IP, that works at high clock rates if needed. It supports full-duplex operation and a configurable baud rate. The IObundle UART has a fixed configuration for the start and stop bits. More flexible licensable commercial versions are available upon request. Download product brief. Get a quote.
IOb-I²S-TDM Audio Transceiver
The IObundle I²S/TDM Transceiver core is a configurable audio interface core with transmission and receiving capabilities. It supports master/slave, internal DMA, multi-channel and several sample sizes and frame formats. The IP is currently supported for use in ASICs and FPGAs. Download product brief. Get a quote.
IOb-SoC, a RISC-V SoC Template
IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or ASIC. It supports stand-alone and boot loading modes, and can use an internal RAM or an external DDR controller via an L1/L2 cache system. A commercial version is also available for IP rights warranty, technical support and customization. Download product brief. Get a quote.