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IObundle demonstrates Edge-AI IP. Porto, 11/27-28/2025: At the 3rd and final General Assembly of the A-IQ-Ready Chips JU project, we demonstrated our RISC-V + CGRA edge AI prototype running on an FPGA. The demo showcased the integration of a RISC-V processor with a coarse-grained reconfigurable accelerator, targeting efficient on-device AI inference for edge applications.
This milestone marks an important step in validating the project’s architecture and design flow, highlighting both performance and flexibility when deploying AI workloads on heterogeneous, open architectures—a big thanks to all project partners for the collaboration throughout the project.
IObundle explains its proprietary Edge-AI flow. Porto, 11/27–28/2025: At the 3rd and final General Assembly of the A-IQ-Ready Chips JU project, we demonstrated our RISC-V + CGRA edge AI design flow. The flow automatically generates RISC-V software, along with a custom CGRA accelerator, tightly controlled by the software, enabling efficient hardware/software co-design for edge AI workloads.
The demonstration highlighted how the flow simplifies the development of heterogeneous systems by bridging software generation and accelerator specialization, while preserving flexibility and programmability. This represents a key outcome of the project, showcasing a practical path toward open, energy-efficient, and scalable AI solutions for the edge.
IObundle explains its proprietary Edge-AI flow. Lisbon, 10/19/2025: José, IObundle’s founder (second from left), had the pleasure of hosting a group of talented Brazilian students supported by the Brazilian Government’s CI Program. During the visit, he shared insights into IObundle’s work in semiconductors and discussed opportunities to strengthen collaboration between academia, industry, and international talent.
The exchange sparked engaging discussions and highlighted the importance of global cooperation in shaping the future of technology. Prof. Guilherme Paim, who accompanied the students, is pictured on the right. Inspiring to see the next generation of engineers so motivated and curious about semiconductor innovation.
IObundle releases new AC-97 IP Core. Lisbon, 08/13/2025: We announce the release of a new AC-97 Controller IP core, providing a complete and compliant interface to AC-97 audio codecs for embedded and SoC-based systems. The IP core implements the AC-97 digital controller and link protocol, enabling reliable control and streaming of audio data between the host system and external codecs.
Designed for straightforward integration in FPGA and ASIC platforms, the AC-97 Controller IP supports seamless connection to standard system buses and fits well in legacy-compatible and cost-sensitive audio designs. This addition expands our audio IP portfolio and reinforces our commitment to delivering robust, reusable IP cores for digital audio and mixed-signal systems.
IObundle speaks at Silicon Saxony Day. Dresden, 06/17/2025: José T. de Sousa, IObundle's CEO, presents our Audio Interface and PNG IP cores today at Silicon Saxony Day, sharing practical insights into the design and integration of reusable IP for modern SoC platforms. The talk highlights how these IP cores address real-world requirements in audio processing and image handling, with a focus on efficiency, interoperability, and ease of integration.
The session provides an opportunity to engage with the Silicon Saxony ecosystem, exchange experiences with industry and research partners, and discuss the role of high-quality IP in accelerating product development. It’s great to be part of an event that brings together innovation, collaboration, and cutting-edge semiconductor technologies.
IObundle releases new ASRC IP Core. Lisbon, 04/29/2025: We are pleased to announce the release of a new Audio Sample Rate Converter (ASRC) IP core, designed to support high-quality and flexible sample-rate conversion in modern digital audio systems. The ASRC IP enables both synchronous and asynchronous conversion across a wide range of audio sample rates, ensuring excellent signal fidelity, low distortion, and low latency for real-time and batch-processing applications.
IObundle speaks at the Open Architectures Workshop. Fundão, 12/03/2024: At a national workshop on open architectures, IObundle’s Pedro Miranda presented and discussed our IOb-SoC open-source architecture and our Python-based IP design framework, Py2HWSW. The session focused on how open and modular system-on-chip architectures, combined with high-level design tools, can accelerate IP development and foster more transparent and reusable hardware designs.
The workshop provided an excellent forum to exchange ideas around open hardware, design productivity, and ecosystem building, and to showcase how IObundle is contributing to the advancement of open architectures in practice.
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